1. Field of Invention
This disclosure relates generally to semiconductor devices, and more specifically to fabricating a non-volatile memory cell.
2. Background
In the field of non-volatile memory devices, various electrically erasable programmable memory devices are widely used in electronic circuits. Some types of electrically erasable programmable memory devices can be programmed and erased repeatedly and are capable of holding charge even after getting disconnected from power supply. Some of these devices utilize discrete charge storing elements called nanoclusters for storing charges in a charge storage location of a transistor. In some cases, the nanoclusters are embedded in an insulator such as a tunnel dielectric (e.g. an oxide).
One type of non-volatile memory cell includes a transistor with a control gate, a charge storing structure and a select gate, which may be referred to as a split gate transistor. In one type of split gate transistor, the charge storing structure includes nanoclusters embedded in an insulating layer to hold the charge. The nanoclusters in the angular gap between the lower portion of the select gate and the dielectric oxide layer over the substrate affect the threshold voltage and speed of the program/erase cycles of the non-volatile memory cell.
In conventional split gate transistors with nanoclusters, the structure of the select gate is such that its lower portion has an angle of 90° with respect to the substrate. Due to this structure, the area near the base of the select gate and the control dielectric is large. Therefore, the nanoclusters formed in this gap may be relatively large in size. The charges stored on these big nanoclusters in the gap may be difficult to erase and require a high erase voltage to discharge them. During the program/erase cycles of the non-volatile memory cell, due to trapping of charges in the gap nanoclusters, the erase voltage required increases with each cycle due to charges being trapped in the gap nanoclusters. This reduces the cycling endurance of the memory cell. Further, the conventional transistors have a thick dielectric layer on the channel. Due to this, read voltage cannot be lowered and cell currents are reduced. This also causes general cell performance to decrease. Thus, there exists a need for reducing the size of gap nanoclusters, so that they are uniform in size with respect to other nanoclusters in the charge storing layer.
Another disadvantage of the vertical select gate structure is that nanoclusters in the charge storing layer get accumulated at the bottom. Due to this the number of nanoclusters that affect the channel during program/erase cycle are more and consequently the threshold voltage (Vt) of program/erase increases. Thus, there exists a need for reducing the number of gap nanoclusters affecting the channel, as well as a need for reducing the effective area of the insulating layer surrounding the nanoclusters that affect the channel.